Thermal-mechanical modelling of power electronic module packaging

In this paper the reliability of the isolation substrate and chip mountdown solder interconnect of power modules under thermal-mechanical loading has been analysed using a numerical modelling approach. The damage indicators such as the peel stress and the accumulated plastic work density in solder interconnect are calculated for a range of geometrical design parameters, and the effects of these parameters on the reliability are studied by using a combination of the finite element analysis (FEA) method and optimisation techniques. The sensitivities of the reliability of the isolation substrate and solder interconnect to the changes of the design parameters are obtained and optimal designs are studied using response surface approximation and gradient optimization metho

Optimizing the reliability of power electronics module isolation substrates

Optimal design of a power electronics module isolation substrate is assessed using a combination of finite element structural mechanics analysis and response surface optimisation technique. Primary failure modes in power electronics modules include the loss of structural integrity in the ceramic substrate materials due to stresses induced through thermal cycling. Analysis of the influence of ceramic substrate design parameters is undertaken using a design of experiments approach. Finite element analysis is used to determine the stress distribution for each design, and the results are used to construct a quadratic response surface function. A particle swarm optimisation algorithm is then used to determine the optimal substrate design. Analysis of response surface function gradients is used to perform sensitivity analysis and develop isolation substrate design rules. The influence of design uncertainties introduced through manufacturing tolerances is assessed using a Monte-Carlo algorithm, resulting in a stress distribution histogram. The probability of failure caused by the violation of design constraints has been analyzed. Six geometric design parameters are considered in this work and the most important design parameters have been identified. Overall analysis results can be used to enhance the design and reliability of the component

On variable frequency microwave processing of heterogeneous chip-on-board assemblies

Variable Frequency Microwave (VFM) processing of heterogeneous chip-on-board assemblies is assessed using a multiphysics modelling approach. The Frequency Agile Microwave Oven Bonding System (FAMOBS) is capable of rapidly processing individual packages on a Chip-On-Board (COB) assembly. This enables each package to be processed in an optimal manner, with temperature ramp rate, maximum temperature and process duration tailored to the specific package, a significant benefit in assemblies containing disparate package types. Such heterogeneous assemblies may contain components such as large power modules alongside smaller modules containing low thermal budget materials with highly disparate processing requirements. The analysis of two disparate packages has been assessed numerically to determine the applicability of the dual section microwave system to curing heterogeneous devices and to determine the influence of differing processing requirements of optimal process parameters

Multi-objective NSGA-II based shape optimisation of the cross-sectional shape of passively cooled heat sinks

Purpose The purpose of the study is to optimise the cross-sectional shape of passively cooled horizontally mounted pin-fin heat sink for higher cooling performance and lower material usage. Design/methodology/approach Multi-objective shape optimisation technique is used to design the heat sink fins. Non-dominated sorting genetic algorithm (NSGA-II) is combined with a geometric module to develop the shape optimiser. High-fidelity computational fluid dynamics (CFD) is used to evaluate the design objectives. Separate optimisations are carried out to design the shape of bottom row fins and middle row fins of a pin-fin heat sink. Finally, a computational validation was conducted by generating a three-dimensional pin-fin heat sink using optimised fin cross sections and comparing its performance against the circular pin-fin heat sink with the same inter-fin spacing value. Findings Heat sink with optimised fin cross sections has 1.6% higher cooling effectiveness than circular pin-fin heat sink of same material volume, and has 10.3% higher cooling effectiveness than the pin-fin heat sink of same characteristics fin dimension. The special geometric features of optimised fins that resulted in superior performance are highlighted. Further, Pareto-optimal fronts for this multi-objective optimisation problem are obtained for different fin design scenarios. Originality/value For the first time, passively cooled heat sink’s cross-sectional shapes are optimised for different spatial arrangements, using NSGA-II-based shape optimiser, which makes use of CFD solver to evaluate the design objectives. The optimised, high-performance shapes will find direct application to cool power electronic equipment

Multi-material heatsink design using level-set topology optimization

In this article we apply a Level-set topological optimization algorithm to the design of multi-material heat sinks suitable for electronics thermal management. This approach is intended to exploit the potential of metal powder additive manufacturing technologies which enable fabrication of complex designs. The article details the state-of-the-art in topological optimization before defining a numerical framework for optimization of two-material and three-material based heatsink designs. The modelling framework is then applied to design a pure copper and a copper-aluminum heatsink for a simplified electronics cooling scenario and the performance of these designs are compared. The benefits and drawbacks of the implemented approach are discussed along with enhancements that could be integrated within the framework. A benchmarking study is also detailed which compares the performance of topologically optimized heat sink against a conventional pin-fin heat sink. This is the first time that topological optimization methods have been assessed for multi-material heat sink design where both conduction and convection are included in the analysis. Hence, the reported work is novel in its application of a state-of-the-art Level-set topology optimization algorithm to design multi-material structures subject to forced convective cooling. This paper is intended to demonstrate the applicability of topological optimization to the design of multi-material heatsinks fabricated using additive manufacturing processes and succeeds in this objective. The paper also discusses challenges, which need to be addressed in order to progress this modelling as a design approach for practical engineering situations. The presented methodology is able to design thermal management structures from a combination of aluminum and copper that perform similarly to pure copper but utilizing less expensive materials resulting in a cost benefit for electronics manufacturers

Damage mechanics-based failure prediction of wirebond in power electronic module

A damage mechanics-based numerical approach for the prediction of the damage evolution in wirebond structures of the power electronic module (PEM) is presented. A simplistic damage evolution model is developed in an in-house finite element code, with a demonstration focused on the analysis of the wirebond damage evolution by thermally induced stresses in PEM subjected to varying thermal loads. The novelty of the proposed methodology is the damage evolution realized at the level of each discretised mesh element of the finite element model of the PEM structure in the numerical approach and the associated impact of damage on the mechanical material properties of that element. A simplified PEM structure is utilised as a case study to demonstrate the proposed damage evolution modelling. The thermal load of each discretised element of the PEM structure was imported from an external thermal code. From the thermally induced stresses, plastic strain rates were approximated and then, using these metrics a damage evolution metric was derived. The damage distribution plot of the wirebond structure for the applied load in the case study indicates that maximum damage accumulation at the heel structure reaches 2.4% of the total damage after 3 seconds. By extrapolating the trendline of damage evolution in wirebond, the time of the structural failure was also predicted. The maximum von Mises stress was observed on the busbar which reaches 64 MPa. The extreme stresses found at the busbar are attributed to the high value of the coefficient of thermal expansion of the busbar materia

Design of additively manufactured heatsinks for power electronics thermal management using adjoint level-set topology optimization

This paper investigates the potential of using the Adjoint Level-set topological optimization approach for design of additively manufactured power electronics heat sinks. Additive manufacturing techniques are readily able to fabricate highly complex metal geometries. This capability could be translated into development of higher performance thermal management solutions if the design methodology to exploit this potential. This study attempts to investigate the ability of topology optimization to meet this requirement. This paper provides a brief review of the current state-of-the-art in the topological optimization field. An overview of the Adjoint Level-set method is presented along with details of the implemented framework. This framework is used to design power electronics heatsinks, considering a combination of materials and fluid flow rates. The analysis is multi-objective, simultaneously considering heat extraction and flow pressure difference. The heat flux into the heatsink is considered to be from two discrete heat fluxes representing active packages within the power module. The cooling channels developed by the topology optimization framework react to the position of the heat sources. Results demonstrating the capability for topological optimization to develop effective thermal management solution are presented. The primary conclusions for the study are that this is an area that is worth of further investigation. Significant challenges need to be addressed, particularly relating to the rapid increase in computational cost as flow rates increase, before this technology can be transitioned to commercial adoptio

Reliability testing and stress measurement of QFN packages encapsulated by an open-ended microwave curing system

In this paper, the influence of microwave curing on the reliability of a representative electronic package is examined by reliability testing and measurement of residual stresses. A LM358 voltage regulator die was mounted to an open Quad Flat No-leads package (QFN) for reliability testing. For the stress measurement, a specifically designed stress measurement die was mounted to the QFN package. The chips were encapsulated with Hysol EO1080 thermosetting polymer material. Curing was performed using an open-ended microwave oven system equipped with in situ temperature control. Three different temperature profiles for microwave curing were selected according to the requested degree of cure and chemical composition of the cured material. A convection cure profile was selected for the control group samples. Thermal cycling and HAST tests were performed on a total number of 80 chips. 95 QFN packages with stress measurement chips were also manufactured. Increased lifetime expectancy of the microwave cured packaged chips was experimentally demonstrated and measured between 62% to 149% increased lifetime expectancy after Temperature Cycling Test (TCT), and between 63% and 331% after highly Accelerated Ageing Test (HAST) and TCT compared to conventionally cured packages. Analysis of specifically designed stress test chips showed significantly lower residual stresses ranging from 26 MPa to 58.3 MPa within the microwave cured packages compared to conventionally cured packaged chips which displayed residual stresses ranging from 54 MPa to 80.5 MPa. This article therefore provides additional confidence in the industrial relevance of the microwave curing system and its advantages compared to traditional convection oven systems

Comparative reliability of inkjet-printed electronics packaging

This article compares the thermomechanical behavior of 3-D inkjet-printed microelectronics devices relative to those fabricated from traditional methods. It discusses the benefits and challenges in the adoption of additive manufacturing methods for microelectronics manufacture relative to conventional approaches. The critical issues related to the design and reliability of additively manufactured parts and systems stem from the change in the manufacturing process and the change in materials utilized. This study uses numerical modeling techniques to gain insight into these issues. This article is an extension of the same topic presented at the 2018 IEEE Electronics Packaging Technology Conference. An introduction providing an overview of the area, covering salient academic research activities and discussing progress toward commercialization is presented. The state-of-the-art modular microelectronics fabrication system developed within the EU NextFactory project is introduced. This system has been used to manufacture several test samples, which were assessed both experimentally and numerically. A full series of JEDEC tests showed that the samples were reliable, successfully passing all tests. The numerical model assessing the mechanical behavior of an inkjet-printed structure during layer-by-layer fabrication is presented. This analysis predicts that the stresses induced by the UV cure process are concentrated toward the extremities of the part and, in particular, in the lower layers which are constrained by the print platform. Subsequently, a model of a multilayer microelectronics structure undergoing JEDEC thermal cycling is presented. The model assesses the differences in mechanical properties between a conventional FR4/copper structure and an inkjet-printed acrylic/silver structure. The model identified that the influence of the sintering process on subsequent material properties, behavior of the inject-printed structure, and reliability of the inject-printed structure is significant. Key findings are that while stresses in the conventional and inkjet boards are relatively similar, the inkjet-printed board exhibits significantly greater deformation than the standard board. Furthermore, the mechanical stresses in the inkjet fabricated board are strongly dependent on the elastic modulus of the sintered silver material, which, in turn, is dependent on the sintering process

Open ended microwave oven for flip-chip assembly

A novel open-ended waveguide cavity resonator for the microwave curing of bumps, underfills and encapsulants is described. The open oven has the potential to provide fast alignment of devices during flip-chip assembly, direct chip attach, surface mount assembly or wafer-scale level packaging. The prototype microwave oven was designed to operate at X-band for ease of testing, although a higher frequency version is planned. The device described in the paper takes the form of a waveguide cavity resonator. It is approximately square in cross-section and is filled with a low-loss dielectric with a relative permittivity of 6. It is excited by end-fed probes in order to couple power preferentially into the TM3,3,k mode with the object of forming nine 'hot-spots' in the open end. Low power tests using heat sensitive film demonstrate clearly that selective heating in multiple locations in the open end of the oven is achievabl